1. Field of the Invention
The present invention generally relates to manufacture of multichip integrated circuit device configurations, and in particular to techniques for assuring that the device sides of chips in such configurations are in the same plane.
2. Background Description
As advances in semiconductor processing occur, the scale of individual integrated circuit devices continues to shrink, making it possible to incorporate increasing amounts of functionality in a single integrated circuit chip. For example, sixteen 1 MBIT Dynamic Random Access Memory (DRAM) chips of equal size in 1984 required a total chip area of 800 mm.sup.2, while a single 16 MBIT design containing the same functionality in 1990 required only 110 mm.sup.2. Thus, although the individual chip size has increased by approximately 50%, the net chip area has been reduced by a factor of 8. Accordingly, as integrated circuit chips are required to incorporate more and more functionality, the size of the chips has been steadily increasing.
However, there are practical problems associated with continually increasing the maximum chip size. A first set of problems relates to the physical limits of present day fabrication equipment. For example, state-of-the-art manufacturing lithography equipment commonly used to expose high resolution patterns through masks onto semiconductor substrates effectively limits chip size to the size of the lithography exposure field of the equipment. The size of the direct exposure field of state-of-the-art manufacturing lithography equipment in the mid 1990s is generally on the order of 25 mm in diameter, allowing square chip design exposure of about 324 mm.sup.2 (18 mm.times.18 mm). Most DRAM chip designs in development are rectangular and tend to be 20 mm.times.10 mm, or larger. While a mask larger than the lithography exposure field of the equipment can be split into multiple smaller masks that are "stitched" together to effectively multiply the size of the lithography exposure field, such "stitching" introduces undesired inaccuracies and occupies valuable space on the semiconductor substrate. A solution to the exposure field/stitching problem is to develop fabrication equipment having a larger exposure field and, therefore, the capability to manufacture larger chips without stitching masks together. However, such a solution would require massive financial investment in research and development.
Additionally, in order for a wafer to produce a large enough number of chips to make the manufacturing of larger chips practical, semiconductor wafers would need to migrate to a larger size, thereby requiring further substantial investment in the development of new crystal pulling equipment, and wafer processing and handling equipment.
Another problem relates to the general trend of wafer yields decreasing with increasing chip size. FIG. 1 summarizes different manufacturing chip yields as a function of the chip edge dimension (square chips). It will be observed that as the chip area increases, the effective chip yields reduce nearly linearly. The different curves relate to different design complexities, with the topmost curve being the least complex and the bottommost curve being the most complex of the three exemplary curves. The decrease in yield with increasing chip size can be attributed to the fact that for the same quality of semiconductor, any defect existing in a larger chip results in an overall greater area waste than is the case with smaller chip wafers. As chip size increases, the cost of manufacturing due to yield degradation becomes prohibitive.
Conventional multi-chip modules (MCM's) avoid the problems associated with producing large chips by combining a plurality of small-sized chips in a larger package. For example, U.S. Pat. No. 4,489,364, assigned to IBM, discloses a ceramic chip carrier for supporting an array of chips by means of solder balls. However, such MCMs tend to be extremely expensive due to their multilayered ceramic features and they require significantly more area than the net overall area of the combined set of chips.
Other similar approaches include the High Density Interconnect (HDI) structure proposed by the General Electric Company and generally described in IEEE magazine, 1991, "A 36-Chip Multiprocessor Multichip Module made with the General Electric High Density Interconnect Technology". However, the HDI technology offers poor positional accuracy of chips, preventing the use of a fixed mask to make chip-to-chip connections, and thereby making the process of interconnecting individual chips extremely time consuming and expensive.
An improved integration scheme for combining, in close proximity, a plurality of semiconductor die units is described in U.S. Pat. No. 5,814,885 to Pogge et al., which provides an integrated circuit package including a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having a conversely matching bottom surface topography to permit self-aligned positioning of the chip on the carrier.
However, there is a further need, within the foregoing integration scheme, to provide for differing chip thicknesses, since the chips which are integrated by the self aligning surface projections or recesses will typically originate from different wafer sources tending to have different wafer thicknesses. Typical device wafers vary in thickness from wafer to wafer within about 1-3 .mu.m. When such wafers are used in a precisely integrated chip process, such thickness variations can result in chip-to-chip non-planarities which adversely affect overall process and product efficiency. Where different chip macros are being placed closely together and then interconnected with standard metallization photo masks, it is desirable to have the device side of the chips be planar to each other.
Specific wafer sorting can reduce thickness variations, but remaining differences can create non-planarities of as much as 1-1.5 .mu.m. Individual chips can be polished to the same thickness, but this becomes difficult on a chip by chip basis and requires unique polishing tool capabilities. Another approach is needed to compensate for variations in wafer thickness.